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tm data device corporation 105 wilbur place bohemia, new york 11716 631-567-5600 fax: 631-567-7358 www.ddc-web.com for more information contact: technical support: 1-800-ddc-5757 ext. 7382 features ? synthesized reference option 1 minute accuracy available (?s? option only) single +5 v power supply 10-, 12-, 14-, or 16-bit programmable resolution small 34-pin ceramic package bit output velocity output eliminates tachometer high reliability single chip monolithic -55c to +125c operating temperature range mil-prf-38534 processing available description the sd-14550 series are small complete low cost hybrid synchro- or resolver-to-digital converters based on a single-chip monolithic. the sd-14550x ?s? option offers synthesized reference circuitry to correct for phase shifts between the reference and signal voltage. the com- pletely self-contained unit offers programmable resolution and +5 vdc operation. the package is a 34-pin, 1.0 x 0.78 x 0.21 inch ceramic package. resolution programming allows selection of 10-, 12-, 14-, or 16-bit modes. this feature allows selection of either low resolution for fast tracking or higher resolution for higher accuracy. the velocity output (vel) from the sd-14550, which can be used to replace a tachometer, is a 4 v signal referenced to analog ground with a linearity of 1% of output voltage. this converter series also offers a built-in-test output (bit ). the sd- 14550 converters are available with operating temperature ranges of 0c to +70c, -40c to +85c and -55c to +125c. these convert- ers are also available with mil-prf-38534 processing. applications with its low cost, small size, high accuracy, and versatile perfor- mance, the sd-14550 series converters are ideal for use in modern high-performance military, commercial and space position control systems. typical applications include radar antenna positioning, nav- igation and fire control systems, motor control, and robotics. ? 1991, 1999 data device corporation sd-14550 series programmable synchro/resolver- to-digital converters make sure the next card you purchase has...
2 data device corporation www.ddc-web.com sd-14550 series rev. h figure 1. sd-14550 series block diagram s1 s2 s3 input option control transformer gain demodulator rh rl r i c i vel integrator hysteresis vco & timing 14/16 bit up/down counter data latches em data el inh s4 bit detector reference conditioner error bit r los b 8 8 dc-dc converter filter 33 f external capacitor +5 v +5 v -5 v a b a "s" option synthesized reference
3 data device corporation www.ddc-web.com sd-14550 series rev. h table 1. sd-14550 series specifications these specs apply over the rated power supply, temperature, and refer- ence frequency ranges; 10% signal amplitude variation, and 10% har- monic distortion. parameter unit value resolution bits programmable 10, 12, 14, or 16 accuracy min 1, 2 or 4, + 1 lsb (see table 4) repeatability lsb 1 max. differential linearity lsb (rh, rl) differential 2 & 11.8 v units 90 v unit 1 max. reference input type sd-14550 voltage range frequency input impedance single ended differential common-mode range sd-14550xs voltage range frequency input impedance single ended differential common-mode range sig/ref phase shift vrms hz ohm ohm vpeak vrms hz ohm ohm vpeak deg. 2-35 360 - 5k 60k 120k 50, 100 transient 2-35 1k - 5k 40k 80k 50, 100 transient 45 max. 10-130 60 (47-5k) 400 (360-5k) 270k min. 540k min. 200, 300 transient ? ? ? ? ? ? signal input characteristics 90 v synchro input (l-l) zin line-to-line zin line-to-ground common-mode voltage 11.8 v synchro input (l-l) zin line-to-line zin line-to-ground common-mode voltage 11.8 v resolver input (l-l) zin line-to-line zin line-to-ground common-mode voltage 2 v direct input (l-l) voltage range max. voltage w/o damage input impedance 2 v resolver input (l-l) zin line-to-line zin line-to-ground common-mode voltage ohm ohm v ohm ohm v ohm ohm v vrms v ohm ohm ohm v 123k 80k 180 max. 52k 34k 30 max. (same for ? s ? option) 140k 70k 30 max. 2 nom, 2.3 max. 25 cont, 100 pk transient 20 m || 10 pf min. ( ? s ? option only) 11k 22k 4.9 max. table 1. sd-14550 series specs. (continued) parameter unit value digital input/output inputs (continued) inhibit (lnh ) enable bits 1 to 8 (em ) enable bits 9 to 16 (el ) outputs parallel data built-in-test drive capability bits ttl cmos logic 0 inhibits; data stable within 0.5 s logic 0 enables; data stable within 150 ns logic 1 = high impedance data high z within 100 ns 16 parallel lines; 2 bytes natural binary angle, posi- tive logic. logic 0 = bit condition. ~ 100 lsbs of error with a filter of 500 s for los. (los and lor for ? s ? option) 50 pf + logic 0; 1 ttl load, 1.6 ma at 0.4 v max logic 1; 10 ttl loads, -0.4 ma at 2.8 v min logic 0; 100mv max. driving logic 1; +5 v supply minus 100 mv min. velocity characteristics (see note 1.) polarity voltage range (full scale) scale factor scale factor tc reversal error linearity zero offset zero offset tc load noise v % ppm/ c % % mv v/ c kohm (vp/v)% positive for increasing angle 4.0 typ. 3.5 min. 10 typ. 20 max. 100 typ. 200 max. 1 typ. 2 max. 0.5 typ. 1 max. 5 typ. 10 max. 15 typ. 30 max. 20 max. 1 typ. 2 max. power supplies nominal voltage voltage tolerance max. voltage w/o damage current ? s ? option v % v ma ma +5 5 +7 30 typ. 35 max. 30 typ. 35 max. temperature range operating -30x -20x -10x storage c c c c 0 to +70 -40 to +85 -55 to +125 -65 to +150 physical characteristics size weight 1.00 x 0.78 x 0.21 (25.4 x 19.81 x 5.33) 0.44 (12.47) in (mm) oz (g) digital input/output logic type inputs resolution control ttl/cmos compatible logic 0 = 0.8 v max. logic 1 = 2.0 v min. loading =10 a max p.u. current source to +5 v || 5 pf max. cmos transient protected. see table 2. notes: 1. refer to table 3 for full-scale tracking rate.
4 data device corporation www.ddc-web.com sd-14550 series rev. h general setup considerations the following recommendations should be considered when using the sd-14550 series converters: 1) the power supply is +5 v dc. 2) direct inputs are referenced to agnd. 3) connect (close to hybrid) pin 31 (analog ground) to pin 7 (gnd). 4) connect a 33 f/10 vdc tantalum filter capacitor externally between pin 5 (filter point) to pin 7 (ground). programmable resolution resolution is controlled by pins 27 and 28. the resolution can be changed during converter operation so that the appropriate res- olution and velocity dynamics can be set as needed. to insure that a race condition does not exist between counting and changing the resolution, the resolution control is latched inter- nally. refer to table 2 for resolution control. bit (built-in-test) this output is a logic line that will flag an internal fault condition or los (loss-of-signal). the internal fault detector monitors the internal loop error and, when it exceeds approximately 100 lsbs, will set the line to a logic 0; this condition will occur during a large-step input and will reset to a logic 1 after the converter settles out. (the error voltage is filtered with a 500 s filter.) bit will set for an over velocity condition because the converter loop cannot maintain input/output sync. bit will also be set if a total los (loss of all signals) occurs. additionally, in the sd-14550xs version, bit will set when a loss-of-reference (lor) condition occurs. theory of operation the sd-14550 series of converters are based upon a single chip cmos custom monolithic. they are implemented using the latest ic technology, which merges precision analog circuitry with digital logic to form a complete high performance tracking synchro/resolver-to-digital converter. converter operation figure 1 is the functional block diagram of the sd-14550 series. the converter operates with a single +5 v dc power sup- ply and internally generates a negative voltage of approximate- ly 5 volts. this negative voltage comes out on pin 5 (filter point) ? see general setup considerations. the converter is made up of three main sections; an input front- end, an error processor, and a digital interface. the converter front-end differs for synchro, resolver and direct inputs. an elec- tronic scott-t is used for synchro inputs, a resolver conditioner for resolver inputs, and a sine and cosine voltage follower for direct inputs. these amplifiers feed the high accuracy control transformer (ct). its other input is the 16-bit digital angle . its output is an analog error angle, or difference angle, between the two inputs. the ct performs the ratiometric trigonometric com- putation of sin cos - cos sin = sin( - ) using amplifiers, switches, logic, and capacitors in precision ratios. the converter accuracy is limited by the precision of the com- puting elements in the ct. in these converters ratioed capacitors are used in the ct, instead of the more conventional precision ratioed resistors. capacitors used as computing elements with op-amps need to be sampled to eliminate voltage drifting. therefore, the circuits are sampled at a high rate to eliminate this drifting and at the same time to cancel out the op-amp off- sets. the error processing is performed using the industry standard technique for type ii tracking r/d converters. the dc error is integrated yielding a velocity voltage which in turn drives a volt- age controlled oscillator (vco). this vco is an incremental inte- grator (constant voltage input to position rate output) which together with the velocity integrator forms a type ii servo feed- back loop. a lead in the frequency response is introduced to sta- bilize the loop and another lag at higher frequency is introduced to reduce the gain and ripple at the carrier frequency and above. table 2. resolution control (a and b) resolution b a 10 bit 0 0 12 bit 0 1 14 bit 1 0 16 bit 1 1
5 data device corporation www.ddc-web.com sd-14550 series rev. h interfacing solid-state buffer protection - transient voltage suppression the solid-state signal and reference inputs are true differential inputs with high ac and dc common rejection, so most applica- tions will not require units with isolation transformers. input impedance is maintained with power off. the recurrent ac peak + dc common mode voltage should not exceed the values in table 1. the 90 v line-to-line systems may have voltage transients which exceed the 300 v specification listed in table 1. these tran- sients can destroy the thin-film input resistor network in the hybrid. therefore, 90 v l-l solid-state input modules may be protected by installing voltage suppressors as shown in figure 2. voltage transients are likely to occur whenever a synchro is switched on and off. for instance, a 1000 v transient can be gen- erated when the primary of a cx or tx input is opened. inhibit and enable timing the inhibit (inh ) signal is used to freeze the digital output angle in the transparent output data latch while the data is being trans- ferred. application of an inhibit signal does not interfere with the continuous tracking of the converter. as shown in figure 3, angular output data is valid 500 nanoseconds maximum after the application of the low-going inhibit pulse. output angle data is enabled onto the tri-state data bus in 2 bytes. this enable msb (em ) is used for the most significant 8 bits and enable lsb (el ) is used for the least significant bits. as no false 180 hangup this feature eliminates the ? false 180 reading ? during instanta- neous 180 step changes; this condition most often occurs when the input is ? electronically switched ? from a digital-to-synchro converter. if the ? msb ? (or 180 bit) is ? toggled ? on and off, a converter without the ? false 180 hangup ? feature may fail to respond. the condition is artificial, as a ? real ? synchro or resolver cannot change its output 180 instantaneously. the condition is most often noticed during wraparound verification tests, simulations, or troubleshooting. synthesized reference the synthesized reference section ( ? s ? option) eliminates errors due to phase shift between the reference and signal inputs. quadrature voltages in a resolver or synchro are by definition the resulting 90 fundamental signal in the nulled out error volt- age (e) in the converter. due to the inductive nature of synchros and resolvers, their output signals lead the reference input sig- nal (rh and rl). when an uncompensated reference signal is used to demodulate the control transformer ? s output, quadrature voltages are not completely eliminated. as shown in figure 1, the converter synthesizes its own internal reference signal based on the sin and cos signal inputs. therefore, the phase of the synthesized (internal) reference is determined by the sig- nal input, resulting in reduced quadrature errors. the synthe- sized reference circuit also eliminates the 180 degree false error null hang up. 100 ns max em or el 150 ns max data data valid high z high z data data valid 500 ns max inhibit rh rl 115 v ref. input cr1 cr3 cr2 1n6071a for 90 v synchro inputs 90 v synchro input s1 hybrid s3 s2 cr1, cr2, and cr3 are in6068a, bipolar transient voltage supressors or equivalent. s1 s3 s2 figure 2. connections for voltage transient suppressors figure 4. enable timing figure 3. inhibit timing
6 data device corporation www.ddc-web.com sd-14550 series rev. h shown in figure 4, output data is valid 150 nanoseconds max- imum after the application of a low-going enable pulse. the tri- state data bus returns to the high impedance state 100 nanosec- onds maximum after the rising edge of the enable signal. dynamic performance a type ii servo loop (kv = ) and very high acceleration con- stants give the sd-14550 superior dynamic performance. transfer function and bode plot the dynamic performance of the converter can be determined from its functional block diagram (figure 1), its transfer func- tion block diagram (figure 5), and its bode plots (open and closed loop - figure 6). values for the transfer function block can be obtained from table 3. the open loop transfer function is as follows: where a is the gain coefficient and b is the frequency of lead compensation 2 s a +1 ( ) b 2 s s +1 ( ) 10b open loop transfer function = -12 db/oct gain = 4 ba 2a -6 db/oct 10b (rad/sec) 2a 2 2 a (rad/sec) f = bw = 3db 2 a (hz) closed loop open loop - gain = 0.4 (b=a/2) (critically damped) figure 6. bode plots error processor resolver input ( ) velocity out digital position out ( ) vco ct s a + 1 1 b s s + 1 10b h = 1 + - e a 2 s 2 s a +1 ( ) b 2 s s +1 ( ) 10b open loop transfer function = where: 2 a = a a 1 2 figure 5. transfer function block diagram table 3. dynamic characteristics device type 60 hz ?s? option input frequency bandwidth (closed loop) ka a1 a2 a b hz hz 1/s 2 1/s 1/s 1/s 1/s 47 - 5k 15 830 0.17 5k 29 14.5 1k - 5k 150 110k 2.47 44.4k 333 166 resolution bits 16 14 12 10 16 14 12 10 tracking rate (rps) typical minimum acceleration ( 1 lsb lag) settling time (179 step max) rps rps deg/s 2 msec 0.5 0.4 11.3 2500 2 1.6 45 1100 8 6.4 180 500 32 25.6 720 400 2.5 2 610 232 10 8 2440 150 40 32 9760 78 160 128 39k 51 400 hz 360 - 5k 56 53k 0.41 41k 130 81 16 14 12 10 2.5 2 93 360 10 8 372 180 40 32 1490 100 160 128 5950 90 table 4. accuracy/resolution version resolution vs accuracy (in lsb?s - see note 2) 10 bit 12 bit 14 bit 16 bit sd-1455x-xx accuracy (minutes) see note 1 4 +1 lsb 2 +1 lsb 2 2 2 2 4 3 13 7 sd-1455x-xs ( ? s ? option) * 1.3 minute (4 lsb) accuracy available for ? s ? option only. inclusive of 1 bit of jitter. note 1: accuracy base measured in 16 bit mode. note 2: accuracy in resolution rounded up to next lsb: lsb in 16 bit mode = 0.3 minutes lsb in 14 bit mode = 1.3 minutes lsb in 12 bit mode = 5.3 minutes lsb in 10 bit mode = 21.1 minutes 4 +1 lsb 2 +1 lsb 1 +1 lsb 2 2 2 2 2 2 4 3 2 13 7 4* accuracy and resolution table 4 lists the total accuracy including quantitation for the var- ious resolutions and accuracy grades. units parameter
7 data device corporation www.ddc-web.com sd-14550 series rev. h 0.780 max (19.81) 0.400 (10.16) 0.800 (20.32) index denotes pin 1 0.210 max (5.33) 1.0 max (25.4) 0.700 (17.78) 0.160 min (4.064) 0.050 (1.27) 0.100 typ (2.54) 0.050 typ (1.27) 0.600 (15.24) 0.018 dia typ (0.46) 16 17 18 19 33 34 2 1 3 32 20 15 numbers for reference only 0.008 (0.20) 0.05 (1.27) 16 eq. sp. @ 0.050 = 0.80 tol noncom typ (1.24 = 20.32) see note 2 0.500 min typ (12.7) 0.100 0.010 typ (2.54 0.25) 0.210 max (5.33) 27 28 1 34 0.780 max (19.81) pin 1 denoted by index mark 1.000 max (25.4) 0.010 0.002 typ (0.25 0.05) pin numbers for reference only 0.018 0.002 typ (0.46 0.05) 0.050 typ (1.27) 0.020 r typ (0.51) figure 8. sd-14550 mechanical outline (flat pack) figure 7. sd-14550 mechanical outline (dip) notes: 1. (s) = synchro; (r) = resolver; (d) = 2 v resolver direct. 2. connect (close to the hybrid) pin 31 to pin 7. 3. connect a 33 f/10 vdc tantalum filter cap from pin 5 to pin 7. bit 5 bit 13 18 19 bit 12 (lsb, 12-bit mode) bit 4 17 16 bit 6 20 bit 11 15 bit 14 (lsb, 14-bit mode) 21 bit 3 14 bit 7 22 bit 10 (lsb, 10-bit mode) 13 bit 15 23 bit 2 12 bit 8 24 bit 9 11 bit 16 (lsb, 16-bit mode) 25 bit 1 (msb) 10 el (enable lsbs) 26 bit (built-in-test) 9 a (resolution control a) 27 em (enable msbs) 8 b (resolution control b) 28 gnd (ground) 7 inh (inhibit) 29 +5 v (power supply) 6 vel (velocity output) 30 filter point 5 agnd (analog ground) 31 n.c. n.c. s4 (r) 4 n.c. 32 sin (d) s3 (s) s3 (r) 3 rl (-reference input) 33 cos (d) s2 (s) s2 (r) 2 function rh (+reference input) pin 34 n.c. s1 (s) s1 (r) pin function 1 table 5. pinouts (dip and flat pack) notes: 1. dimensions are in inches (mm). 2. lead identification numbers are for reference only 3. lead cluster shall be centered within 0.005 (0.13) of outline dimensions. lead spacing dimensions apply only at seating plane. 4. pin material meets solderability requirements to mil-std-202e, method 208c. 5. case is hermetically sealed ceramic package. notes: 1. dimensions are in inches (mm). 2. lead cluster shall be centralized about case centerline within 0.010 (2.54).
8 data device corporation www.ddc-web.com sd-14550 series rev. h ordering information sd-1455x x x - x x x x supplemental process requirements: s = pre-cap source inspection l = pull test q = pull test and pre-cap inspection k = one lot date code w = one lot date code and pre-cap source y = one lot date code and 100% pull test z = one lot date code, pre-cap source and 100% pull test blank = none of the above accuracy: 2 = 4 min + 1 lsb 4 = 2 min + 1 lsb 5 = 1 min + 1 lsb (available with ? s ? option only) reliability grade: 0 = standard ddc processing, no burn-in (see table on next page.) 1 = mil-prf-38534 compliant 2 = b* 3 = mil-prf-38534 compliant with pind testing 4 = mil-prf-38534 compliant with solder dip 5 = mil-prf-38534 compliant with pind testing and solder dip 6 = b* with pind testing 7 = b* with solder dip 8 = b* with pind testing and solder dip 9 = standard ddc processing with solder dip, no burn-in (see table on next page.) temperature grade/data requirements: 1 = -55 c to +125 c 2 = -40 c to +85 c 3 = 0 c to +70 c 4 = -55 c to +125 c + variables test data 5 = -40 c to +85 c + variables test data 8 = 0 c to +70 c + variables test data options: x = none s = synthesized reference package type: d = dip f = flat pack input options: 0 = 11.8 v, synchro, 400 hz 1 = 11.8 v, resolver, 400 hz 2 = 90 v, synchro, 400 hz 3 = 2 v, direct, 400 hz 4 = 90 v, synchro, 60 hz input options (?s? option): 1 = 11.8 v, resolver, 1 khz 3 = 2 v, resolver (differential), 1 khz *standard ddc processing with burn-in and full temperature test ? see table on next page.
9 data device corporation www.ddc-web.com sd-14550 series rev. h standard ddc processing test mil-std-883 method(s) condition(s) inspection 2009, 2010, 2017, and 2032 ? seal 1014 a and c temperature cycle 1010 c constant acceleration 2001 a burn-in 1015, table 1 ?
10 data device corporation www.ddc-web.com sd-14550 series rev. h notes:
11 data device corporation www.ddc-web.com sd-14550 series rev. h notes:
12 h-10/01-250 printed in the u.s.a. the information in this data sheet is believed to be accurate; however, no responsibility is assumed by data device corporation for its use, and no license or rights are granted by implication or otherwise in connection therewith. specifications are subject to change without notice. 105 wilbur place, bohemia, new york, u.s.a. 11716-2482 for technical support - 1-800-ddc-5757 ext. 7382 headquarters, n.y., u.s.a. - tel: (631) 567-5600, fax: (631) 567-7358 southeast, u.s.a. - tel: (703) 450-7900, fax: (703) 450-6610 west coast, u.s.a. - tel: (714) 895-9777, fax: (714) 895-4988 united kingdom - tel: +44-(0)1635-811140, fax: +44-(0)1635-32264 ireland - tel: +353-21-341065, fax: +353-21-341568 france - tel: +33-(0)1-41-16-3424, fax: +33-(0)1-41-16-3425 germany - tel: +49-(0)8141-349-087, fax: +49-(0)8141-349-089 japan - tel: +81-(0)3-3814-7688, fax: +81-(0)3-3814-7689 world wide web - http://www.ddc-web.com data device corporation registered to iso 9001 file no. a5976 r e g i s t e r e d f i r m ? u

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